One of the major disadvantages associated with IGFET inverter circuits has been their relatively poor current driving capability. The IGFET device is a modulated resistor and consequently IGFET circuits exhibit large RC time constants, particularly during their turn-off transition when driving capacitive loads. This deficiency becomes substantial when the IGFET inverter is used as an off-chip driver for a large scale integrated circuit, charging secondlevel package capacitances. Several IGFET inverter circuits are available from the prior art. They are briefly reviewed in what follows.
The simplest IGFET inverter circuit consists of a resistor connected in series with an enhancement mode IGFET. The circuit is completed by connecting the source of the IGFET to a reference or ground potential and the resistor to a drain voltage supply. The output voltage of this circuit is taken at the interconnection node between resistor and IGFET. When the enhancement mode transistor is in its off state, the output is at the drain voltage supply which is typically referred to as the logic "one" level. When the enhancement mode IGFET is switched on, the output is pulled down (N-channel) to a level near the reference voltage, which is typically referred to as the logic "zero" level. The logic "zero" level depends on the ratio between the resistance of the enhancement mode IGFET and the load resistor. Although the use of a simple resistor for load has the advantage that one of the output levels is the voltage of the drain supply, the circuit is not practical in integrated circuit form because a diffused region on the chip having resistance sufficiently large to provide a low level of power dissipation, occupies a large surface area.
One substitute for a diffused load resistor is an enhancement mode IGFET, whose gate and drain terminals are connected to the drain voltage supply. However, this circuit has the disadvantage that the logic "one" level of the output can only reach a potential equal to the drain voltage less one threshold voltage of the load IGFET, which is typically greater than one volt. Another disadvantage is that the output current of the load device decreases very rapidly as the magnitude of the output node voltage, which is also the potential of the source terminal of the load IGFET, increases because the load transistor is always biased in its saturated range. This type of inverter circuit is referred to as saturated load.
Another implementation of a load device for an IGFET inverter circuit uses an enhancement mode IGFET, whose gate is connected to a gate voltage supply having a greater magnitude than the drain voltage supply. With this type of voltage bias, the load device is always biased in its linear range and the undesirable drop in load current found in saturated loads is eliminated. Accordingly, this type of inverter circuit is known as linear load. The disadvantage with this approach is that it requires an additional voltage supply.
Another approach by the prior art is the use of a depletion mode IGFET with its gate and source electrically shorted to provide a load current characteristic with more current drive than the previously described load elements. An inverter circuit using this type of load has an enhancement mode IGFET with the same channel conductivity as the depletion mode load device to connect the output node to a source voltage supply. The gate of the enhancement mode device serves as input for the inverter circuit. Because of the gate-to-source short of the depletion mode device, its current output remains substantially constant as the output voltage transitions toward the drain voltage supply, thus enhancing the switching speed of the inverter circuit.
Another IGFET inverter circuit employed in the prior art uses a pair of complementary IGFET devices (CMOS): an N-channel enhancement mode transistor connected to the least positive voltage supply and a P-channel enhancement mode transistor connected to the most positive voltage supply, with the common drains being the output. The gates of the transistors are connected together and receive the input signal. When the input signal is down, the N-channel enhancement mode device is turned off and the P-channel enhancement mode device is turned on so that the output is at the level of the most positive supply voltage. When the input signal is high, the N-channel device is on and the P-channel device is off and the output is at the level of least positive supply voltage.
Since one of the devices of the pair is always off during their steady state, this type of circuit is sometimes categorized as a dynamic type to suggest that it dissipates power only during its switching transients. This is in contrast with all the aforementioned circuits which dissipate power during both their transient and steady state and belong then to the static type of circuit.
A solution to the particular problem of providing IGFET chips with off chip driver circuits having sufficiently large output current to drive second level package capacitances, is to use bipolar transistor devices for the off chip driver in a hybrid IGFET bipolar chip. This solution has not been widely employed because of the higher costs associated with the extra processing needed for bipolar fabrication.